Physical Security Analysis of Embedded Devices

Baris Ege

Promotor: prof.dr. B.P.F. Jacobs (RU)
Copromotor: dr. L. Batina (RU)
Radboud Universiteit Nijmegen
Date: 5 July 2016, 10:30


As more and more of our personal data is stored and processed by electronic systems, security evaluations of such systems has become a necessity rather than a choice in today’s world. Even if a protocol or a cryptographic primitive is theoretically secure, security vulnerabilities can be introduced in their implementation. Side channel attacks exploit such vulnerabilities and can be mounted using widely accessible equipments with ease, if countermeasures are not utilized in the implementation. Therefore, any product that implements cryptography should go through a rigorous security evaluation which also covers its physical behaviour. This thesis focuses on the physical security evaluations of cryptographic implementations.

In Chapter 2, we compare different theoretical metrics which attempt to quantify the security of a cryptographic algorithm against differential side channel attacks. We show that some of these metrics fail to capture the level of security against differential side channel attacks. Additionally, we show that the security of a cryptographic algorithm against differential side channel attacks may vary depending on whether the input or the output data is used by the attacker.

In Chapter 3, we revisit the topic of exploiting side channel leakage in the frequency domain. Our mathematical derivations and experiments suggest that the signal trend (a component in a side channel signal that is constant and shared among independent experiments) can affect the success rate of a side channel attack in the frequency domain. Moreover, we show that the signal to noise ratio can be increased in the frequency domain if the attacker can manipulate the signal trend.

In Chapter 4, we introduce a new approach to side channel collision attacks in an attempt to relax the assumptions required for correlation based side channel analysis. We further show that, using this approach, we can significantly improve an attack on a class of low entropy masking schemes.

In Chapter 5, we investigate how ambient temperature can affect the vulnerability of a device to clock glitches. We show that increased temperature makes the target device more vulnerable to clock glitch attacks. We also present for the first time in the literature that an instruction can be repeated if a clock glitch can be carefully timed.

In Chapter 6, we investigate the security of test compression algorithms. With increased complexity of the modern electronic chips, their structural testing is becoming more challenging. Test compression is a solution which is widely used by manufacturers to save time and keep the test quality high. However, contrary to the assumptions made in the literature, such systems do not automatically provide security. We show that even when industrial countermeasures are employed, classical differential scan attacks can compromise the security of a chip under some conditions.